The present invention relates to the design of high speed counters, and more particularly relates to high speed counters having feed back paths for determining the next output count based upon the present count.
All counters which count the occurrence of electrical impulses, such as clock pulses, in a binary fashion have a plurality of binary output signals whose state toggles, or changes from one signal level to its complement, in a set sequence upon the receipt of the next electrical impulse. High speed counters are known in which the state of the output signals are fed back to circuitry in the counter to determine which of the output signals should be toggled with the receipt of the next electrical impulse to be counted, such that the correct counting sequence may be maintained.
U.S. Pat. No. 3,064,890 by Butler, issued Nov. 20, 1962 for "Parallel Input Fast Carry Binary Counter with Feedback Resetting Means," discloses a high speed circuit having a feedback means and bistable elements, wherein the counter counts in sequence from 0 to N-1, and then recycles back to 0.
U.S. Pat. No. 3,517,318 by McDermond, issued June 23, 1970 for "Synchronous Counter," discloses a counter having a plurality of cascaded binary stages each of which, except the first, is driven by the previous stages and an input source through a NAND gate.
U.S. Pat. No. 3,706,043 by Reinert, issued Dec. 12, 1972 for "Synchronous Parallel Counter With Common Steering Of Clock Pulses To Binary Stages," discloses a parallel counter constructed as an integrated circuit with a plurality of pairs of NAND gates forming binary stages, and a steering circuit including input NAND gates associated with the binary stages. The steering circuit includes coupling from the outputs of the binary stages to the inputs of the higher order input NAND gates, and also couplings from the outputs of the input NAND gates to reset inputs of the lower order binary stages.
U.S. Pat. No. 3,753,127 by Rowe, issued Aug. 14, 1973 for "Pseudosynchronous Counter," discloses a counter which uses ripple counters, and provides a synchronous output through the use of a buffer stage which is loaded at the end of a clock pulse at which time the count will have settled down.
U.S. Pat. No. 3,849,635 by Freedman, issued Nov. 19, 1974 for "High Speed Programmable Counter" discloses a high speed counter wherein final counts of a cycle are counted in an auxiliary counter to provide time for presetting stages in the counter.
U.S. Pat. No. 4,433,372 by Eichrodt et al., issued Feb. 21, 1984 for "Integrated Logic MOS Counter Circuit," discloses a multi-stage logic circuit having gates to produce carry signals between stages, where the gates which transfer the carry signals are designed as transfer-gates.
U.S. Pat. No. 4,464,774 by Jennings, issued Aug. 7, 1984 for "High Speed Counter Circuit," discloses a counter circuit having feedback latches in cascade, and which monitors a carry-in signal for selectively causing the latchs to toggle.